This invention is related to digital processing systems using Dynamic Random Access Memory (DRAM), and particularly to the emulation of next generation dram technology.
For standard page mode Dynamic Random Access Memory (DRAM), the addressing of the memory array is broken up into row and column addresses by a memory controller. The row and column addresses are multiplexed over the same bus, and are captured by the DRAM with Row Address Strobe (RAS) and Column Address Strobe (CAS) lines. In DRAM employing square addressing, the number of row address bits is equal to the number of column address bits. For example, a xe2x80x9c16 Mbxc3x974 bit 12/12 DRAMxe2x80x9d represents a DRAM having a storage capacity of 64 Megabits (Mb) employing square addressing with 12 row address bits and 12 column address bits (12/12).
Each new generation of DRAM technology provides a greater storage capacity than the previous generation. A successive generation of DRAM typically has four times the storage capacity of the previous generation. For example, a current generation DRAM may have a storage capacity of 4 Mbxc3x974 bits, while a next generation DRAM may have a storage capacity of 16 Mbxc3x974 bits. In order to achieve the best price performance for a particular memory design, it is important that the design use the DRAM generation that offers the lowest cost per bit of storage.
Additionally, it would be desirable for the design to easily accommodate the next generation DRAM component, so as to provide a simple and inexpensive transition into that technology when it eventually becomes the lowest cost per bit of storage design solution. However, as a result of space limitations on the circuit board, it is typically not feasible to utilize discrete current generation DRAM components as xe2x80x9ctemporaryxe2x80x9d replacements for a next generation DRAM component since approximately four times as much board space is required for the discrete devices, and extensive card redesign would be needed to migrate to the next generation device. In addition, there are differences in the addressing schemes used by the current and next generation DRAMs. A current generation 4 Mbxc3x974 DRAM, for example, may have square addressing with 11 row address bits and 11 column address bits (11/11), while a next generation 16 Mbxc3x974 DRAM may have square addressing with 12 row address bits and 12 column bits (12/12). It is clear that two additional address bits are needed to address the next generation DRAM. As a result, extensive redesign of the DRAM controller would be necessary to accommodate the addressing scheme of the next generation DRAM.
The use of stacked DRAM components to conserve circuit board space is well known. For example, U.S. Pat. No. 5,371,866 issued on Dec. 6, 1994 to Cady, et al. teaches the use of a stacked DRAM device utilizing a quad RAS decoding scheme wherein address bits from the address bus are used to access the stacked component. However, Cady et al. requires that the addressing scheme for the current generation DRAMs be utilized, thus failing to emulate a next generation component.
U.S. Pat. No. 5,590,071 issued on Dec. 31, 1996 to Kolor et al. (""071 patent) facilitates the emulation of a next generation DRAM by utilizing a component that includes a plurality of DRAMs having a cumulative memory capacity that is at least equal to the capacity of the DRAM component that is to be emulated. The ""071 patent permits the use of a common controller to access the next generation DRAM component as well as the current generation multiple DRAM component so as to facilitate migration to the next generation component when such a migration becomes economically expedient. The invention utilizes the additional bits from the controller""s address signal that are required to address the next generation DRAM, but are not utilized in addressing any one of the lower density DRAMs in the current generation multiple DRAM component. These additional bits are decoded to direct DRAM control signals such as RAS and CAS or WRITE and Output Enable so as to permit one of the plurality of DRAMs to be accessed. The ""071 patent discloses the steering of DRAM control signals such as RAS and CAS on to output lines from a decoder such that only one of the plurality of DRAMs in the current generation component receives both a RAS and a CAS signal. For example, the ""071 patent teaches the emulation of a 16 Mbxc3x974 bit 12/12 DRAM using a quad RAS, dual CAS stacked component including 4 Mbxc3x974 bit 11/11 DRAMs. The stacked component has four independent RAS lines and two independent CAS lines, which are accessible as pins at the package level. The additional row address bit is decoded and used to direct the RAS signals over two of the four RAS lines, and the additional column address bit is decoded and used to direct the CAS signal over one of the two CAS lines. The RAS and CAS lines are arranged such that only one current generation DRAM in the stacked component receives both a RAS and a CAS signal, thereby selecting that DRAM.
The ""071 patent permits migration to a next generation DRAM without altering wiring on the printed circuit board or changing the memory controller used to access the DRAM component. However, the method and apparatus disclosed therein for a DRAM having square addressing is not applicable to stacked components having four independent RAS lines and only one CAS line, such as the 32 pin TSOJ stacked DRAM package manufactured by International Business Machines Corporation (IBM) under model number 42G9062.
The above stated problems and related problems of the prior art are solved with the principles of the present invention, the emulation of a high capacity DRAM component via a single component which includes a plurality of lower memory capacity DRAMs having a cumulative memory capacity greater than or equal to the memory capacity of the DRAM component that is being emulated.
The invention takes advantage of the fact that an address bus for the higher capacity DRAM will contain extra row and column address bits as compared an address bus for each of the plurality of lower capacity DRAMS. The extra row address bit from the memory controller is decoded by decoding logic to direct the DRAM control signal to activate a group of DRAMs from the plurality of lower capacity DRAMs. The extra column address bit is then decoded by the decoding logic to de-activate all but one of the group of DRAMs previously activated. Thus, only one of the lower capacity DRAMs remains active to receive the address signal for the lower capacity DRAM.
The invention allows the emulation of the high memory capacity DRAM component using a quad RAS, single CAS component that utilizes the industry standard footprint for the high memory capacity DRAM component to permit migration thereto without requiring a redesign of the circuit board. Furthermore, the invention provides the ability to use the same addressing scheme for the component containing the plurality of lower memory capacity DRAMs as would be used for the high memory capacity component, thus permitting migration to the high memory capacity component using the same DRAM controller used to access the current generation component including the plural lower memory capacity DRAMs.